1. Field of the Invention
The present invention relates to a packaging chip packaged by a packaging wafer and a method of manufacturing the packaging chip, and more particularly, to a packaging chip packaged using a packaging wafer including a seed layer stacked on an inner side of a viahole and a method of manufacturing the packaging chip.
2. Description of the Related Art
Electronic packaging chips used in various electronic products include micro electronic circuits and thus may be damaged by external impacts. Thus, when such a packaging chip is manufactured, a packaging process must be performed to package the packaging chip so that the packaging chip has physical function and shape so as to endure an external impact. In particular, packaging must be performed on a wafer level to make electronic products small and high performance. In general, a packaging wafer having a predetermined shape is bonded to a wafer including a circuit module to perform the packaging on the wafer level. A packaging chip is supplied with power from an external source so as to perform a specific operation. Thus, packaging must be performed so that an external power source is connected to an internal electronic circuit.
For this purpose, there is used a method of forming a viahole penetrating a packaging wafer and then connecting an internal electronic circuit to an external power source through the viahole using wires. However, if the wires are used, minute dust may flow into the packaging chip through the viahole and signal loss may occur through the wires.
Thus, there has been developed a method of manufacturing a connecting electrode penetrating a packaging wafer to connect an internal electronic circuit to an external power source through the connecting electrode. The connecting electrode is manufactured using a method of forming a viahole penetrating the packaging wafer to stack a seed layer and then plating the viahole using the seed layer. However, a plating speed varies at each portion of the viahole, thus the viahole is not completely filled. As a result, cracks or voids may slightly occur in the viahole. If voids occur, impurities inside the voids rust, which may break down the packaging chip. The impurities inside the voids may be heated by a current supplied from an external source and thus damaged. If cracks occur, minute dust flows into an element from the outside, and thus the element may malfunction.
To prevent these problems, there has been developed a method of forming a seed layer only inside a viahole and plating an inside of the viahole using the seed layer to manufacture a connecting electrode. However, the seed layer is formed only at a low portion, and a plating speed becomes slow. This increases cost. As a result, the unit cost of a packaging chip is increased. Also, cracks may occur, or the packaging chip may be damaged due to a low adhesive strength between a packaging wafer and the connecting electrode. Thus, the manufacturing yield of packaging chips is decreased.